74AUP2G00

Low-power dual 2-input NAND gate

应用领域

The 74AUP2G00 provides dual 2-input NAND function.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

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产品详情

特性

Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:

JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)

ESD protection:

HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V

Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	fmax (MHz)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74AUP2G00DC	Production	0.8 - 3.6	CMOS	± 1.9	8.3	70	2	ultra low	-40~125	203	34.1	113	VSSOP8
74AUP2G00GN	Production	0.8 - 3.6	CMOS	± 1.9	8.3	70	2	ultra low	-40~125	238	10.6	148	XSON8
74AUP2G00GS	Production	0.8 - 3.6	CMOS	± 1.9	8.3	70	2	ultra low	-40~125	276	10.8	146	XSON8
74AUP2G00GT	Production	0.8 - 3.6	CMOS	± 1.9	8.3	70	2	ultra low	-40~125	327	6.1	157	XSON8
74AUP2G00GX	Production	0.8 - 3.6	CMOS	± 1.9	8.3	70	2	ultra low	-40~125	-	-	-	X2SON8

门

74AUP2G00

应用领域

特性

参数类型